CS222 - COMPUTER ARCHITECTURE AND ORGANIZATION
Professor: Russell C. Bjork Fall semester, 2000-2001
Office: McDonald 217 x4377 MWF 1:00-2:00 pm
Hours: MWF 2:10-3:10 PM; Lab: Tues 9:45-12:45
Th 1:30-4:30 PM and by appointment
HANDOUT #1: SYLLABUS - 8/30/00
PREREQUISITE: CS221
COURSE OBJECTIVES:
In general, this course is intended to familiarize you with the way that
computer systems are built up from the fundamental building blocks to form
complete systems.
In particular, upon completion of this course you should be able to:
1. Describe the architecture, organization and major components of a typical
"Von Neumann architecture" computer.
2. Describe and use a typical CISC (the VAX) and RISC (MIPS) architecture.
3. Write and run simple programs in machine language and assembly language.
4. Describe the functionality typically embodied by an instruction set,
including various instruction format and addressing mode options.
5. Describe the implementation of basic instruction-set level functionality by
means of register-transfer level operations.
6. Describe the organization of a CPU, including the options of hard-wired
control and microprogramming.
7. Describe the implementation of the system bus and the memory and I/O
subsystems.
8. Interface IO devices to a simple microprocessor bus system.
9. Discuss some current trends in computer architecture (e.g. parallelism).
TEXT: Patterson, David A and John L. Hennessy. Computer Organization
& Design: The Hardware/Software Interface (2nd ed).
(San Francisco: Morgan Kaufmann, 1998)
ON RESERVE: Clements, Alan. Principles of Computer Hardware. (Boston: PWS, 1993)
Levy, Henry M. and Richard Eckhouse. Computer Programming and
Architecture: The VAX-11. (Bedford, MA: Digital Press, 1980)
COURSE REQUIREMENTS AND EVALUATION:
The primary goal of this course is for you to gain familiarity with the
architecture and implementation of a modern computer.
The first half of the course will focus on architecture, by way of machine and
assembly language programming. We will use the VAX as our major focus in this
part, but we will also compare its architecture to that of the MIPS chips (used
in our SGI workstations.) The VAX is the ultimate expression of CISC
architecture, and MIPS is a typical RISC, so between them we will see something
of the range of modern architectures. We will also take a brief look at other
architectural alternatives toward the end of this half of the course. Our goal
here is not so much gaining facility in assembly language programming as it is
understanding computer architecture at the instruction-set level.
During the second half of the course, we will learn how the capabilities that
are present at the instruction-set level are actually implemented in
hardware - completing the study of computer hardware that was begun in CS221.
As with other Computer Science courses, much of the learning will take place in
the laboratory as you develop the various skills listed in the Course
Objectives. For the first half of the course, our laboratories will focus on
software - specifically machine and assembly language programming, primarily
using the VAX. During the second half of the course, laboratories will be
hardware-oriented, and you will have the opportunity to work with a one-board
computer and to interface various devices to it.
In view of the complexity of some of the material, it is absolutely imperative
that you keep up on your reading and your homework, and that you come to class
prepared to ask questions about things you don't understand. Prior to each
class period you should carefully read the assigned material in the textbook.
Because the material is more technical than in some courses, you will probably
find a greater than normal need to obtain personal help from the instructor.
Please feel free to seek this.
COURSE REQUIREMENTS AND EVALUATION:
1. You will be expected to read most of the textbook, as assigned in the topic
schedule below. Reading assignments should be completed BEFORE the class
hour in which the topic is discussed. Lecture presentations will assume that
you have read the text, and it is expected that your participation in the
class will reflect that fact. However, our classroom discussion will not
rigidly follow the order of material in the text, nor will it be confined to
material covered there.
2. Ten problem sets will be distributed during the semester, and will be
due as shown in the course schedule. Note that these will be fairly
substantial assignments; you would do well to work on the problems as the
material is covered in class, rather than waiting until just before the set
is due to tackle the whole assignment. Solutions to each problem set will
be posted and/or discussed in class on the due date. Each problem set will
be worth 3% of the final course grade (30% total for the 10 sets).
Credit for problem sets will be awarded on the basis of the completeness and
correctness of your solutions, with a minimum of 75% credit guaranteed
for a reasonably complete attempt at solving each problem, even if the answer
is not correct.
Set # Material covered
1 Performance; The VAX Architecture
2 Arithmetic and Logical Instructions; Program Control
3 Addressing Modes
4 Procedures
5 Macros and Conditional Assembly
6 CPU Architectural Alternatives
7 CPU Internals; Control; Microprogramming
8 Pipelining; Overall System Structure
9 Parallel IO; Interrupts; DMA; Serial IO and Networks
10 Cache and Virtual Memory Systems; Parallelism
The following guidelines should be observed when doing these homework sets:
a. Homework sets will be due at the start of class on the date indicated.
Late homework sets will NOT be accepted.
b. Homework sets must be done on one side only of 8-1/2 x 11 paper, and pages
must be stapled in problem-number order. Problems must be numbered, and
final answers (where appropriate) should be highlighted. (Homework sets
not conforming to these standards will be returned ungraded.)
c. You may work together with another student on homework, provided each
of you works on each problem.
d. Where an exercise calls for writing a program, it is sufficient to write
it out by hand; you need not enter it into the computer.
3. Weekly labs will parallel the lectures. You will work on these in teams of
two.
a. Lab requirements will be handed out on the preceeding Friday, and should
be read BEFORE you come to lab. Most lab sessions will begin with a brief
quiz on this reading.
b. Writeups for labs will be due at the start of class on the the following
day, at which time a quiz based on what you learned in lab may be
given. NOTE WELL THAT WRITEUPS ARE REQUIRED TO BE A TEAM EFFORT.
c. Each lab writeup and its associated quiz(zes) will be worth 2.5% of
the final course grade (30% total for the twelve labs having formal
writeups due). The emphases of the labs are as follows:
(Tentative - subject to change)
Lab Emphasis
1 VAX Machine Language Programming
2 The Assembler, Linker, and Debugger
3 Arithmetic Operations; Overflow
4 Addressing Modes
5 Procedures; Recursion
6 MIPS Assembly Language
7 Introduction to the Z80 microprocessor and MPF-I (no writeup or quiz)
8 Using the MPF-I system software
9 Instruction timing
10 Microprogramming
11 Parallel IO interfacing
12 Busy-waiting and Interrupt-driven IO
13 DMA IO
4. A mid-term examination (worth 20% of the course grade) and a final
examination (worth 20%) will be given as shown in the course schedule. Each
exam will assume familiarity with material in the text, covered in lecture,
and/or used in homework problems or labs. Exams will be open book
(course text only), open notes.
5. Final grade computation: Homework 30%
Labs 30%
Exams 40%
-----
100%
The following are minimum guararanteed grades for the averages indicated:
93% - 100%: A 90% - 92.9%: A-
87% - 89.9%: B+ 83% - 86.9%: B 80% - 82.9%: B-
77% - 79.9%: C+ 73% - 76.9%: C 70% - 72.9%: C-
67% - 69.9%: D+ 63% - 66.9%: D 60% - 62.9%: D-
POLICY STATEMENT ON EXTENSIONS AND INCOMPLETES:
1. Extensions of the due dates for homework or projects will be given in the
event of extenuating circumstances (such as illness, personal emergency)
IF you submit a brief written request to the professor as soon as
possible after the circumstances arise. This request will be initialled
(if approved) and will be returned to you. You must attach it to the
piece of work for which the extension was granted.
2. A grade of Incomplete will be given without penalty IF you are unable to
complete the course work by the last day of the term due to major illness or
other similar emergency. Again, a written request should be submitted. Such
a request will only be granted if you are substantially up-to-date with your
course work and were making good progress in the course up to the time that
the difficulty arose. Of course, you must complete all work for the course
by the midpoint of the next semester in accordance with College policy.
3. A grade of Incomplete with a penalty of one letter grade to be applied in the
final grade computation MAY be given if you are unable to complete all the
course work for reasons other than those noted above. You must make a
written request, and your progress in the course, class attendance etc. will
be taken into consideration in determining whether to grant it. Again, you
must complete all work for the course by the end of the next term.
ATTENDANCE POLICY:
Regular class attendance is expected of all students, and class attendance will
be recorded. Students who miss more than three classes during the semester
should expect to see their final grade reduced by 1% for every class missed over
three, and students who miss more than 12 classes will fail the course
automatically. Note that the allowance of missing three classes is meant to
cover unavoidable absences due to illness, field trips, athletic contests etc,
and these allowed absences should be saved for that purpose. There is no such
thing as an "excused absence" except in case of unusual hardship situations such
as being hospitalized for a period of time. Also, absence from class on the day
before or after a school holiday will be counted as a double absence, and each
late to class may be counted as half an absence.
You may ask the professor to waive this policy for you if you earned an A in the
prerequisite course, or if you have an A average in this course as of the
mid-term exam. However, the policy will be reimposed if your subsequent work
deteriorates - in which case the allowed absences will be prorated.
TENTATIVE SCHEDULE OF TOPICS:
Date Topic(s) Reading Written
Work Due
W 8/30 Course Introduction; Architecture and ch. 2
Organization; Performance
PART I: COMPUTER ARCHITECTURE
F 9/1 Introduction to the VAX and VAX Levy pp 21-33,
Machine Language Programming using 55-70, 82-93
Register, Absolute, Immediate and (20-33, 69-84,
Relative Addressing 101-115)
W 9/6 Introduction to VAX Assembly Language; Appendix A LAB 1 DUE
Symbolic Labels and Storage Allocation §A.1-A.4
Directives; Levy pp 33-52
Using VAX Assembly Language and DEBUG (36-66)
F 9/8 Arithmetic and Logical Instructions; Review §3.1-3.4
Condition Codes
M 9/11 (ctd) HOMEWORK 1 DUE
W 9/13 Program Control Instructions §3.5 LAB 2 DUE
Levy pp 55-62, 103-110
(69-77, 118-125)
F 9/15 (ctd)
M 9/18 Additional Addressing Modes Levy pp 62-93 HOMEWORK 2 DUE
(77-115)
W 9/20 (ctd) LAB 3 DUE
F 9/22 (ctd)
M 9/25 Procedures and Parameter Passing §3.6 HOMEWORK 3 DUE
Levy pp 110-133
(125-150)
W 9/27 (ctd) LAB 4 DUE
F 9/29 (ctd)
M 10/2 Macros and Conditional Assembly Levy pp 133-143 HOMEWORK 4 DUE
(150-159)
W 10/4 (ctd) LAB 5 DUE
F 10/6 Interrupts, Traps, Exceptions; Levy pp 276-283
The VMS Condition-Handling Facility (293-299); Handout
M 10/9 Other CPU Architectures: 0,1,2 and 3 HOMEWORK 5 DUE
address machines; CISCs vs RISCs
W 10/11 (ctd) LAB 6 DUE
F 10/13 Review and Catch Up
M 10/16 MIDTERM EXAM (Through VAX Interrupts, Traps, Exceptions)
W 10/18 No class (professor attending OOPSLA Conference)
PART II: COMPUTER ORGANIZATION
M 10/23 CPU Implementation: The Register §5.1-5.3
Transfer Level; Internal Busses through p. 356
W 10/25 (ctd) HOMEWORK 6 DUE
(No writeup for
Lab 7 required)
F 10/27 CPU Control Options; Hardwired and §5.3-5.4;
Microprogrammed Control Appendix C
§C.1-C.2
M 10/30 (ctd) §5.5-5.6; C.3-C.7
W 11/1 (ctd) §5.8-5.11 LAB 8 DUE
F 11/3 Pipelining §6.1-6.3
M 11/6 (ctd) §6.4-6.8; HOMEWORK 7 DUE
6.10-6.13
W 11/8 Overall System Organization §8.4 LAB 9 DUE
F 11/10 (ctd)
M 11/13 (ctd)
W 11/15 Introduction to IO Devices §8.1-8.3 LAB 10 DUE
and Interfacing; Parallel IO
F 11/17 Interrupt-driven and DMA IO §8.5-8.11
M 11/20 (ctd) HOMEWORK 8 DUE
Tu 11/21 No lab (just in case you need something to be thankful for :-) )
M 11/27 Serial IO; Introduction to Clements
Computer Networks ch. 9
W 11/29 (ctd) LAB 11 DUE
F 12/1 Memory System Organization and §7.1-7.3
Management; Cache and Virtual Memory
M 12/4 (ctd) §7.4-7.5 HOMEWORK 9 DUE
W 12/6 (ctd) §7.7-7.10 LAB 12 DUE
F 12/8 Parallelism and Multiprocessing §9.1-9.3
M 12/11 (ctd) §9.4-9.11
W 12/13 Review and Catch up LAB 13 DUE
Tu 12/19 - FINAL EXAM - 2-4 pm HOMEWORK 10 DUE
FINAL LAB
CHECKOUT DUE
Note: "Levy" and "Clements" are books on reserve. Levy pages are 1st ed (2nd ed)
Copyright ©2000 - Russell C. Bjork